Nanoelectronics and Computing

We have active programs focused on the development of nanowire devices, arrays and systems for information processing based on the bottom-up paradigm. The Lieber group is a leader in design and realization of 2- and 3-dimensional circuits and nanoprocessors that offer unique opportunities and challenges compared to existing top-down approaches being explored by others today. Areas of current research interest include the following:

  • Nanowire nanoelectronic devices.  We are pursuing studies of nonvolatile or programmable nanowire devices, including field-effect transistors (FETs) and resistive switches, that can be implemented in a cross-bar architecture. The particular emphasis of our studies is on pushing fundamental limits of the devices (e.g., how small?) and developing new modes of function.
  • Nanowire hierarchical organization. Effective assembly methods are critical to bottom-up and hybrid approaches for building nanocircuits. The Lieber group is committed to improving existing and developing entirely new methods that can lead to the controllable assembly of nanowire building blocks in a material-independent manner in two and three dimensions.
  • Nanocircuits and nanoprocessors. We are pursuing studies of nanowire-based circuits with the goal of demonstrating stand-alone programmable nanocircuits and nanoprocessor systems. To exploit the unique properties of our programmable nanowire devices, we are exploring scalable system architectures in which both the locations and interconnections of nanodevices are programmed post-fabrication. This type of architecture, which is based on unit logic tile, leads naturally to nanoprocessor systems consisting of arrays of interconnected logic tiles. Our major current effort is on developing the tiled architecture in 2D, although 3D nanocircuits and processors represent definite future goals.
The Nanowire
Long coherent spin qubit in a Ge/Si heterostructure nanowire. Scanning electron micrograph of a spin qubit device. The nanowire runs horizontally underneath a gate oxide. Inset, High resolution TEM image shows a typical core/shell nanowire.
Two integrated programmable nanowire logic circuit tiles on a glass substrate.
Two integrated programmable nanowire logic circuit tiles on a glass substrate. These building blocks can be constructed via bottom-up assembly on diverse substrates such as transparent or flexible plastics.